Over the recent years, with advanced micronization of LSI, circuit characteristics have been greatly influenced by accuracy of physical quantities of shapes of layout patterns, layout positions, etc of circuit elements, or scatters in these physical quantities in a manufacturing process. Further, there has been proposed a method of taking the influence thereof into a prediction of the circuit characteristics and optimizing the circuit characteristics.
Conventional technologies are not, however, sufficient for optimizing the circuit characteristics of a whole design target circuit including a multiplicity of elements and wirings due to a heavy load in terms of a calculation quantity. For example, a circuit design includes performing a layout of a gate dimension and a gate width in the way of taking account of a balance between a current driving force of each transistor and a load. A technology of determining the optimal gate dimension and gate width in the design target circuit as a whole is not yet, however, actualized.